Numerically controlled delay lines (NCDLs) are used wherever a signal needs to be delayed by a quantum that is directly proportional to a “delay control number”. In most cases the delayed signal is a clock that is used to drive certain flip-flops of a system. For example, DDR-DRAM-controllers widely deploy NCDLs to provide a 90 degree shift to read data register clock signals, so that data capture occurs at the center of the data valid window.
Scan design is one of the most effective and widely used designs for testability techniques. Based on its capability to provide high fault coverage for complex integrated circuits, scanning is effectively used to screen out parts with manufacturing defects. The highest manufacturing test quality or best fault coverage is achieved when all nodes in a device under test are controllable and observable. A node is controllable if the node can be driven to a specified logic value by setting primary inputs to specific values. A sequential cell is scan controllable when the cell can be set to a known state by serially shifting in specific logic values. A node is observable if a fault at the node can be propagated to primary outputs where response can be measured. A sequential cell is scan observable when the cell state can be observed by serially shifting out data.
However, the output clock signal from an NCDL can be uncontrollable in scan test mode in certain cases. For example, where an NCDL is used to control flip flops, the clock reaching the flip-flops can be uncontrollable in scan test mode. Even when the logic controlling the NCDL is stitched in a scan chain, the value attained in the capture phase may cause a change in the delay control number. The possible change in the delay control number causes the clock signal to have an unpredictable time of arrival. The variable time of arrival of the clock signal poses difficulties in capturing the test pattern response of the flip-flops.
Additionally, the clock output of the NCDL is not observable at a scan flip-flop (pseudo-primary output). This causes the delay chain combinatorial structure to remain uncovered by the scan. In applications where fine granularity as well as high total delay is required, the delay chains can have huge combinatorial structures. The inability to cover the combinatorial structure of the delay chain may result in a substantial portion of the chip/core being uncovered and untested.
Further limitations and disadvantages of conventional and traditional approaches will become apparent, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.